The Mips R10000 superscalar microprocessor

cache refills early. he Mips RlOOOO is a dynamic, superscalar microprocessor that implements T the 64-bit Mips 4 instruction set architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully-pipelined, low-latency execution units. Instructions can be fetched and executed speculatively beyond branches. Instructions graduate in order upon completion. Although execution is out of order, the processor still provides sequential memory consistency and precise exception handling. The RlOOOO is designed for high performance, even in large, real-world applications with poor memory locality. With speculative execution, it calculates memory addresses and initiates cache refills early. Its hierarchical, nonblocking memory system helps hide memory latency with two levels of set-associative, write-back caches. Figure 1 shows the RlOOOO system configuration, and the RlOOOO box lists its principal features. Out-of-order superscalar processors are inherently complex. To cope with this complexity, the RlOOOO uses a modular design that locates much of the control logic within regular structures, including the active list, register map tables, and instruction queues.